1. Technical Field
Embodiments relate to the deposition of a silicon oxide layer of the same thickness on silicon regions and silicon-germanium regions (SiGe) of the same substrate. Embodiments more specifically relate to the deposition of a silicon oxide layer forming the gate insulator of P-channel MOS transistors on silicon-germanium and of N-channel MOS transistors on silicon.
2. Discussion of the Related Art
In integrated circuits, MOS transistors of various types are generally formed, especially MOS transistors with a low operating voltage and MOS transistors with a high operating voltage generally intended to be used for integrated circuit output stages.
For MOS transistors of high operating voltage, the gate insulator is provided to comprise a silicon oxide layer having a thickness on the order of 5 nm, while this thickness is only on the order of 2 nm for MOS transistors of low operating voltage. Thus, to form the silicon oxide of MOS transistors of high operating voltage, it is preferred to use silicon oxide deposition techniques while, for MOS transistors of low operating voltage, the silicon oxide is generally formed by thermal growth.
In CMOS (“Complementary Metal-Oxide-Semiconductor”) technologies, to improve the characteristics of P-channel MOS transistors, a solution is to form the P-channel MOS transistors in an SiGe layer. In such technologies, deposition techniques have to be used to form a silicon oxide layer above silicon and above silicon-germanium, especially due to the different oxidation kinetics of Si and SiGe and to the segregation of Ge on the oxidation front.
FIGS. 1A to 1C illustrate successive steps of the forming of a gate insulator of an N-channel MOS transistor and of a P-channel MOS transistor, on a same substrate, in the case of MOS transistors of high operating voltage.
FIG. 1A is a cross-section view of the upper portion of a silicon substrate 1. In the upper portion of silicon substrate 1, insulation areas 3 delimit the regions where transistors are desired to be formed. Insulation areas 3, for example, are shallow trenches filled with silicon oxide, commonly designated as STI (“Shallow Trench Insulation”).
The right-hand portion of FIG. 1A shows a region 5 on which an N-channel MOS transistor is desired to be formed and the left-hand portion of the drawing shows a region 7 on which a P-channel MOS transistor is desired to be formed. In region 7, a silicon-germanium to layer 9 which penetrates into silicon substrate 1 and reaches the same level has been formed.
FIG. 1B illustrates a step of deposition of a silicon oxide layer above the silicon and silicon-germanium regions of substrate 1. Before depositing the silicon oxide layer, a chemical cleaning of the upper surfaces of the Si and SiGe regions with hydrofluoric acid is performed, followed by an oxidizing bath, for example, in a sulfuric peroxide mixture (SPM). The chemical cleaning is especially used to remove possible contaminants present at the surface of silicon and of silicon-germanium. In the chemical cleaning, a silicon oxide layer 11, called chemical oxide, having a thickness smaller than 1 nm, generally forms above the Si and SiGe regions. After the chemical cleaning of the upper surfaces of the Si and SiGe regions, a silicon oxide layer 12 is deposited above chemical oxide layer 11, by low pressure chemical vapor deposition (LPCVD) or rapid thermal chemical vapor deposition (RTCVD).
FIG. 1C illustrates a step of forming, above silicon oxide layer 12, a stack 13 of insulating material layers, comprising one or several silicon nitride layers and materials of high dielectric permittivity. The forming of this stack, and especially of the silicon nitride layer, implies anneal steps at temperatures approximately ranging from 900 to 1000° C.
FIG. 2 is a diagram showing, for various trials, in abscissas, measurements (eSiO2/Si) of the thickness, in angstroms or tenths of a nanometer, of the silicon oxide layer above the silicon regions and in ordinates, measurements (eSiO2/SiGe) of the thickness of the silicon oxide layer above the silicon-germanium regions. The measurements have been performed once all the insulator forming and anneal steps have been carried out, respectively in the case where silicon oxide layer 12 has been deposited by an LPCVD method and in the case of an RTCVD method.
It can be observed in FIG. 2 that the silicon oxide thicknesses on silicon-germanium regions are greater than on silicon regions. It can also be observed that the silicon oxide thickness difference on the silicon and silicon-germanium regions is greater in the case where silicon oxide region 12 has been deposited by an LPCVD method than in the case of an RTCVD method. In the case of a silicon oxide layer 12 deposited by RTCVD, the silicon oxide thickness difference on silicon and silicon-germanium regions is approximately 0.2 nm, against more than 0.5 nm in the case of an LPCVD method.
Such thickness differences are considered as partly resulting from the initial chemical silicon oxide and partly resulting from the actual deposited silicon oxide.
The thickness differences of the silicon oxide layer on the silicon regions of N-channel MOS transistors and on the silicon-germanium regions of P-channel MOS transistors raise an to issue, since they result in differences in voltage behavior, leakage currents, and on-state current, and more generally in differences in terms of performance.